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general description the max9973/max9974 fully integrated, high-perfor- mance, dual-channel pin electronics driver/compara- tor/load (dcl) with built-in level-setting digital-to-analog converters (dacs) are ideally suited for memory and soc automatic test equipment (ate) applications. each channel includes a three-level pin driver, a win- dow comparator, dynamic clamps, a 1k load, and seven independent level-setting dacs. the driver features a wide voltage range and high-speed operation, includes high-impedance and active-termina- tion (3rd-level drive) modes, and is highly linear even at low voltage swings. additionally, the driver provides high- speed differential multiplexer control inputs, with internal termination resistors that are compatible with ecl, lv- pecl, lvds, and gtl. the window comparators provide extremely low timing variation over changes in slew rate, pulse width, or overdrive voltage, and have open-collec- tor outputs. when high-impedance mode is selected, the dynamic clamps provide damping of high-speed device- under-test (dut) waveforms. the load facilitates fast con- tact testing when used in conjunction with the comparators, and functions as a pullup for open-drain/collector dut_ outputs. the max9973/ max9974 are configured through a serial interface. the max9973/max9974 differ in two aspects: the posi- tion of the exposed heat slug and the pin arrangement. the max9973g/max9974g comparator outputs sink 8ma (typ), while the max9973h/max9974h compara- tor outputs sink 16ma (typ). the devices are available in a 64-pin (10mm x 10mm x 1.00mm) tqfp-ep pack- age with an exposed paddle on top (max9973) or bot- tom (max9974) for heat removal. power dissipation is only 700mw per channel. the full operating voltage range is -1.5v to +6.5v. operation is specified at an internal die temperature of +40? to +100?, and fea- tures a temperature monitor output. applications memory testers soc testers features ? 600mbps at 3v high speed ? 700mw per channel extremely low power dissipation ? -1.5v to +6.5v wide voltage range ? 200mv to 8v wide voltage swing range ? 10na (max) low-leakage mode ? integrated termination on-the-fly (3rd-level drive) ? integrated voltage clamps ? passive load or pullup ? very low timing dispersion ? minimal external component count ? spi tm -compatible serial control interface max9973/max9974 dual driver/comparator/load with internal dacs ________________________________________________________________ maxim integrated products 1 ordering information 19-0690; rev 0; 1/07 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. note: devices are available in both leaded and lead-free packages. specify lead free by adding a + symbol at the end of the part number when ordering. * future product?ontact factory for availability. ** ep-idp = exposed paddle (inverted die paddle). ? ep = exposed paddle. part pin-package pkg code output sink current m a x9 9 7 3 gc cb 64 tqfp-ep-idp** (10mm x 10mm x 1.00mm) c64e-13r 8ma m ax9973h c c b* 64 tqfp-ep-idp** (10mm x 10mm x 1.00mm) c64e-13r 16ma m a x9 9 7 4 gc cb* 64 tqfp-ep ? (10mm x 10mm x 1.00mm) ?ma m ax9974h c c b* 64 tqfp-ep ? (10mm x 10mm x 1.00mm) 16ma pin configuration appears at end of data sheet. spi is a trademark of motorola inc.
max9973/max9974 dual driver/comparator/load with internal dacs 2 _______________________________________________________________________________________ absolute maximum ratings * dissipation wattage values are based on still air with no heat sink. actual maximum power dissipation is a function of heat ext raction technique and may be substantially higher. v cc to gnd ............................................................-0.3v to +11v v ee to gnd...............................................................-6v to +0.3v v cc - v ee ................................................................-0.3v to +17v v dd to gnd ..............................................................-0.3v to +5v v t0 , v t1 to gnd .......................................................-0.3v to +5v dgs to gnd .......................................................................?.7v dut_ to gnd.........................................................-2.5v to +7.5v data_, ndata_, rcv_, nrcv_ to gnd .................-2.5v to +5v data_ to ndata_, rcv_ to nrcv_ .....................................?v data_, ndata_, rcv_, nrcv_ to vterm_......................?.5v sclk, din, cs , rst , load to gnd .........-0.3v to (v dd + 0.3v) temp to gnd ...........................................................-0.2v to +5v all other pins to gnd ......................(v ee - 0.3v) to (v cc + 0.3v) dut_ short circuit to -1.5v to +6.5v..........................continuous power dissipation (t a = +70?) max997_gccb (derate 125mw/? above +70?)......10.0w* storage temperature range .............................-65? to +150? junction temperature .....................................................+150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units driver dc characteristics (r l 10m , unless otherwise noted; includes dac error) v dhv_ v dlv_ = -1.5v, v dtv_ = +1.5v -1.45 +6.50 v dlv_ v dhv_ = +6.5v, v dtv_ = +1.5v -1.50 +6.45 output voltage range v dtv_ v dhv_ = +6.5v, v dlv_ = -1.5v -1.50 +6.50 v v dhv_ v dhv_ = +3v, v dlv_ = -1.5v, v dtv_ = +1.5v ?0 v dlv_ v dlv_ = 0v, v dhv_ = +6.5v, v dtv_ = +1.5v ?0 output offset voltage v dtv_ v d t v _ = + 1.5v , v d h v _ = + 6.5v , v d l v _ = - 1.5v ?0 mv output-voltage temperature coefficient (notes 2, 3) dhv_, dlv_, dtv_ ?5 ?00 ?/? v dhv_ v dlv_ = -1.5v, v dtv_ = +1.5v, v dhv_ = 0 and +4.5v 0.998 1 1.002 v dlv_ v dhv_ = +6.5v, v dtv_ = +1.5v, v dlv_ = 0 and +4.5v 0.998 1 1.002 gain v dtv_ v dhv_ = +6.5v, v dlv_ = -1.5v, v dtv_ = 0 and +4.5v 0.998 1 1.002 v/v stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics (v cc = +9.75v, v ee = -4.75v, v dd = 3.3v, v dhv_ = +3v, v dlv_ = 0, v dtv_ = +1.5v, sc1 = sc0 = 0, v chv_ = +2.0v, v clv_ = +1.0v, v cphv_ = +7.2v, v cplv_ = -2.2v, v vterm = v t_ = +1.8v, r t = 50 || 1pf, t j = +70?, unless otherwise noted. all temperature coefficients are measured at t j = +40? to +100?, unless otherwise noted.) (note 1)
max9973/max9974 dual driver/comparator/load with internal dacs _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units v d lv _ = - 1.5v , v d tv _ = + 1.5v , v d h v _ = 0, + 0.75v , + 1.5v , + 2.25v , + 3v ? v d h v_ = + 6.5v , v d tv_ = + 1.5v , v d lv_ = 0, +0.75v , +1.5v, + 2.25v , + 3v ? 0 to 3v relative to calibration points at 0 and 3v v d lv _ = - 1.5v , v d h v _ = + 6.5v , v d tv _ = 0, + 0.75v , + 1.5v , + 2.25v , + 3v ? v d lv _ = - 1.5v , v d tv _ = + 1.5v , v d h v _ = - 1.25v and + 6.5v ? v d h v_ = + 6.5v , v d tv_ = + 1.5v , v d lv_ = - 1.5v and + 6.25v ? linearity error full range relative to calibration points at 0 and 3v v d lv _ = - 1.5v , v d h v _ = + 6.5v , v d tv _ = - 1.5v and + 6.5v ? mv v dhv_ to v dlv , v d lv _ = 0, v d tv _ = 1.5v , v d h v _ = 0.2v and 6.5v ? v dlv_ to v dhv , v d h v_ = + 5v , v d tv_ = + 1.5v , v d lv_ = - 1.5v and + 4.8v ? v dtv_ to v dlv_ and v dhv , v d h v _ = + 3v , v d lv _ = 0, v d tv _ = - 1.5v and + 6.5v ? v dhv_ to v dtv , v d tv _ = + 1.5v , v d lv _ = 0, v d h v _ = + 1.6v and + 3.0v ? crosstalk v dlv_ to v dtv , v d tv_ = + 1.5v , v d h v_ = + 3v , v d lv_ = 0 and + 1.4v ? mv term voltage dependence on data_ v dtv_ = +1.5v, v dhv_ = +3v, v dlv_ = 0, data_ = 0 and 1 ? mv v dhv_ , v dhv_ = 3v, v cc and v ee independently varied over full range 40 v dlv_ , v dlv_ = 0, v cc and v ee independently varied over full range 40 dc power-supply rejection v dtv_ , v dtv_ = 1.5v, v cc and v ee independently varied over full range 40 db v dlv_ /v dut_ = -1.5v/+6.5v, data_ = 0 -120 -60 v dhv_ /v dut_ = +6.5v/-1.5v, data_ = 1 +60 +120 v dtv_ /v dut_ = -1.5v/+6.5v, rcv_ = 1 -120 -60 dc drive current limit v dtv_ /v dut_ = +6.5v/-1.5v, rcv_ = 1 +60 +120 ma dc output resistance (note 4) 48 50 52 electrical characteristics (continued) (v cc = +9.75v, v ee = -4.75v, v dd = 3.3v, v dhv_ = +3v, v dlv_ = 0, v dtv_ = +1.5v, sc1 = sc0 = 0, v chv_ = +2.0v, v clv_ = +1.0v, v cphv_ = +7.2v, v cplv_ = -2.2v, v vterm = v t_ = +1.8v, r t = 50 || 1pf, t j = +70?, unless otherwise noted. all temperature coefficients are measured at t j = +40? to +100?, unless otherwise noted.) (note 1)
max9973/max9974 dual driver/comparator/load with internal dacs 4 _______________________________________________________________________________________ electrical characteristics (continued) (v cc = +9.75v, v ee = -4.75v, v dd = 3.3v, v dhv_ = +3v, v dlv_ = 0, v dtv_ = +1.5v, sc1 = sc0 = 0, v chv_ = +2.0v, v clv_ = +1.0v, v cphv_ = +7.2v, v cplv_ = -2.2v, v vterm = v t_ = +1.8v, r t = 50 || 1pf, t j = +70?, unless otherwise noted. all temperature coefficients are measured at t j = +40? to +100?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units d ata_ = 1, v d h v_ = 3v , v d lv_ = 0, v d tv_ = 1.5v, i dut_ = 1ma to 40ma 12 dc output resistance variation d ata_ = 0, v d h v_ = 3v , v d lv_ = 0, v d tv_ = 1.5v, i dut_ = -1ma to -40ma 12 ac characteristics (r dut _ = 50 to ground) (note 5) dynamic drive current (note 6) 60 ma v dlv_ = 0, v dhv_ = 0.1v 30 v dlv_ = 0, v dhv_ = 1v (note 2) 40 75 v dlv_ = 0, v dhv_ = 3v (note 2) 50 175 drive-mode overshoot v dlv_ = 0, v dhv_ = 5v (note 2) 50 275 mv termination-mode overshoot (note 7) 0 mv to within 100mv, v dhv_ = 5v, v dlv_ = 0 0.25 to within 50mv, v dhv_ = 3v, v dlv_ = 0 0.25 settling time (note 8) to within 25mv, v dhv_ = 0.5v, v dlv_ = 0 0.25 ns timing characteristics (notes 5, 9) data to output; v dhv_ = 3v, v dlv_ = 0 2 3 d r i ve to hi g h i m p ed ance, hi g h i m p ed ance to d r i ve ( n ote 10) ; v d h v _ = + 1v , v d lv _ = - 1v 1.7 4 drive to term 2.7 4 prop delay ( n ote 2) term to drive 1.7 4 ns t lh vs. t hl 50 100 prop delay match (note 2) drivers within package; same edge 40 100 ps p r op - d el ay tem p er atur e c oeffi ci ent (note 2) 1 5 ps/? v dhv_ = 1v, v dlv_ = 0, 2ns to 23ns pulse width 10 100 v dhv_ = 3v, v dlv_ = 0, 3ns to 22ns pulse width 10 100 prop delay change vs. pulse width (note 2) v dhv_ = 5v, v dlv_ = 0, 4ns to 21ns pulse width 20 100 ps prop delay change vs. common mode v dhv_ - v dlv_ = 1v, v dhv_ = 0 to 6v, (using a dc block) 25 ps d r i ve to hi g h i m p ed ance vs. hi g h i m p ed ance to d r i ve; v d h v _ = 1v , v dlv_ = -1v (note 11) 0.2 h i g h i m p ed ance vs. data (note 2) 0.4 d r i ve to ter m vs. ter m to d r i ve; v d h v _ = 3v , v d l v _ = 0 , v d t v _ = 1 .5 v ( n o te 12 ) 1 delay match terminate vs. data 0.7 ns
max9973/max9974 dual driver/comparator/load with internal dacs _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units 0.2v p - p p rog r am m ed, v d h v_ = 0.2v, v d lv_ = 0, 20% to 80% 0.20 1v p - p p r og r am m ed , v d h v _ = 1v , v d lv _ = 0, 10% to 90% 0.35 0.50 0.75 3v p-p programmed, v dhv_ = 3v, v dlv_ = 0, 10% to 90%, trim condition 1.0 1.2 1.5 rise and fall time 5v p-p programmed v dhv_ = 5v, v dlv_ = 0, 10% to 90% 2.0 ns 0.2v p - p p r og r am m ed , v d h v _ = 0.2v , v d lv _ = 0, 20% to 80% 40 1v p - p p r og r am m ed , v d h v _ = 1v , v d lv _ = 0, 10% to 90% 150 3v p-p programmed, v dhv_ = 3v, v dlv_ = 0, 10% to 90 200 rise and fall time matching 5v p-p programmed, v dhv_ = 5v, v dlv_ = 0, 10% to 90% (note 2) 250 ps s c 1 = 0, s c 0 = 1, v d h v _ = 3v , v dlv_ = 0, 20% to 80% 75 s c 1 = 1, s c 0 = 0, v d h v _ = 3v , v dlv_ = 0, 20% to 80% 50 slew rate relative to sc1 = sc0 = 0 s c 1 = 1, s c 0 = 1, v d h v _ = 3v , v dlv_ = 0, 20% to 80% 25 % 0.2v p-p programmed, v dhv_ = 0.2v, v dlv_ = 0 0.4 1v p - p p rog r am m ed v d h v_ = 1v , v d lv_ = 0 ( note 2) 0.7 2 3v p - p p rog r am m ed v d h v_ = 3v , v d lv_ = 0 ( note 2) 1.5 2.5 minimum pulse width (note 13) positive or negative 5v p - p p rog r am m ed v d h v_ = 5v , v d lv_ = 0 ( note 2) 2.4 3.5 ns 0.2v p - p p r og r am m ed , v d h v _ = 0.2v , v d lv _ = 0 2900 1v p-p programmed, v dhv_ = 1v, v dlv_ = 0 1300 3v p-p programmed, v dhv_ = 3v, v dlv_ = 0 600 data rate (note 14) 5v p-p programmed, v dhv_ = 5v, v dlv_ = 0 400 mbps rise and fall time, drive to term v dhv_ = 3v, v dlv_ = 0, v dtv_ = 1.5v, measured 10% to 90% of waveform 1.6 ns rise and fall time, term to drive v dhv_ = 3v, v dlv_ = 0, v dtv_ = 1.5v, measured 10% to 90% of waveform 0.7 ns electrical characteristics (continued) (v cc = +9.75v, v ee = -4.75v, v dd = 3.3v, v dhv_ = +3v, v dlv_ = 0, v dtv_ = +1.5v, sc1 = sc0 = 0, v chv_ = +2.0v, v clv_ = +1.0v, v cphv_ = +7.2v, v cplv_ = -2.2v, v vterm = v t_ = +1.8v, r t = 50 || 1pf, t j = +70?, unless otherwise noted. all temperature coefficients are measured at t j = +40? to +100?, unless otherwise noted.) (note 1)
max9973/max9974 dual driver/comparator/load with internal dacs 6 _______________________________________________________________________________________ parameter symbol conditions min typ max units comparator dc characteristics input voltage range -1.5 +6.5 v differential input voltage ? v minimum hysteresis rhyst_ = open 0 mv maximum hysteresis r rhyst _ = 2.5k 10 mv input offset voltage v dut_ = 1.5v ?0 mv input-voltage temperature coefficient (notes 2, 15) ?5 ?00 ?/? common-mode rejection ratio cmrr v dut_ = -1.5v, +6.5v 50 70 db linearity error, 0 to 3v v dut_ = 0, 1.5v, 3v (note 16) ? ? mv linearity error, full range v d u t_ = - 1.5v , 0, + 1.5v , + 3v , + 6.5v ( n ote 16) ? ?0 mv power-supply rejection ratio psrr v dut_ = -1.5v and +6.5v 50 75 db ac characteristics (notes 17?0) minimum pulse width (note 21) 0.85 ns prop delay 1.2 2 ns prop-delay temperature coefficient (note 2) 2.6 5 ps/? prop delay match high/low vs. low/high; absolute value of delta for each comparator (note 2) 40 100 ps prop delay dispersion vs. common-mode input common-mode input -1.4v to +6.4v (note 22) 20 ps 3ns to 22ns pulse width, 500ps t rise , positive and negative pulses 10 60 prop delay dispersion vs. pulse width (note 2) 2ns to 23ns pulse width 10 100 ps prop delay dispersion vs. slew rate slew rate = 0.5v/ns to 2v/ns 10 ps 100m v < v c _v _ < 900m v , d r i ver i n ter m m od e, p eak- to- p eak w i thi n thi s w i nd ow 40 50m v < v c _v __ < 950m v , d r i ver i n ter m m od e, peak-to-peak within this window 60 waveform tracking (note 23) 100m v < v c _v _ < 900m v , d r i ver i n hi g h i m p ed ance, p eak- to- p eak w i thi n thi s w i nd ow 100 ps logic outputs (ch_, nch_, cl_, ncl_) termination voltage v t _ 0 3.5 v output voltage compliance set by i out , r term , and v t_ -0.5 v t_ v differential rise time 20% to 80% (note 2) 200 400 ps differential fall time 20% to 80% (note 2) 200 400 ps electrical characteristics (continued) (v cc = +9.75v, v ee = -4.75v, v dd = 3.3v, v dhv_ = +3v, v dlv_ = 0, v dtv_ = +1.5v, sc1 = sc0 = 0, v chv_ = +2.0v, v clv_ = +1.0v, v cphv_ = +7.2v, v cplv_ = -2.2v, v vterm = v t_ = +1.8v, r t = 50 || 1pf, t j = +70?, unless otherwise noted. all temperature coefficients are measured at t j = +40? to +100?, unless otherwise noted.) (note 1)
max9973/max9974 dual driver/comparator/load with internal dacs _______________________________________________________________________________________ 7 parameter symbol conditions min typ max units termination resistor value v t_ to ch_, nch_, cl_, ncl_ 48 52 output high voltage v t_ = 0, 3.5v v t_ - 0.1 v t_ - 0.02 v t_ v output low voltage v t_ = 0, 3.5v v t_ - 0.55 v t_ - 0.4 v t_ - 0.35 v output voltage swing v t_ = 0, 3.5v 350 400 450 mv dynamic clamps c p hv _; i d u t _ = - 1ma, cp h v _ = -0.4v and + 6.6v , cplv_ = -1.5v -0.3 +6.5 functional clamp range c p lv _; i d u t _ = 1m a, c p lv _ = - 1.6v and + 5.4v , cphv_ = +6.5v -1.5 +5.3 v maximum programmable cphv_ i dut _ = 0ma (note 24) 7.2 7.5 v minimum programmable cplv_ i dut _ = 0ma (note 24) -2.5 -2.2 v i d u t_ = - 1m a, c ph v _ = + 1.5v , c p lv _ = - 1.5v 50 offset voltage i d u t_ = + 1m a, c plv _ = + 1.5v , c p hv _ = + 6.5v 50 mv offset-voltage temperature coefficient 0.5 mv/? i dut _ = - 1m a, c p h v _ = + 1.5v , c p lv _ = - 1.5v 40 power-supply rejection i d u t _ = + 1ma, cp lv _ = +1.5v, c ph v _ = + 6.5v 40 db high-clamp voltage gain cphv_ = 0, +6.5v, cplv_ = -1.5v 0.99 1.01 v/v low-clamp voltage gain cplv_ = -1.5v, +5.3v, cphv_ = +6.5v 0.99 1.01 v/v voltage gain matching 1% voltage-gain temperature coefficient 100 ppm/? i dut _ = -1ma, cphv_ = 0, +1.5v, +3.25v, +5v, +6.5v ?0 linearity i d u t _ = + 1m a, c p lv _ = - 1.5v , + 0.5v , + 2.25v , + 4v , +5.3v ?0 mv c p h v _ = 0, c p lv _ = - 1.5v , r l = 0 to + 6.5v -120 -60 static output current c p lv _ = + 5v, c ph v _ = + 6.5v , r l = 0 to - 1.5v 60 120 ma high clamp, v cphv_ = 2.5v, i dut _ = -5ma and -15ma 48 55 dc impedance low clamp, v cplv_ = 2.5v, i dut _ = 5ma and 15ma 48 55 high clamp, i dut _ = -20ma and -30ma, cphv_ = +2.5v, cplv_ = -1.5v ? dc impedance variation (note 25) low clamp, i dut _ = 20ma and 30ma, cplv_ = 2.5v, cphv_ = 6.5v ? electrical characteristics (continued) (v cc = +9.75v, v ee = -4.75v, v dd = 3.3v, v dhv_ = +3v, v dlv_ = 0, v dtv_ = +1.5v, sc1 = sc0 = 0, v chv_ = +2.0v, v clv_ = +1.0v, v cphv_ = +7.2v, v cplv_ = -2.2v, v vterm = v t_ = +1.8v, r t = 50 || 1pf, t j = +70?, unless otherwise noted. all temperature coefficients are measured at t j = +40? to +100?, unless otherwise noted.) (note 1)
max9973/max9974 dual driver/comparator/load with internal dacs 8 _______________________________________________________________________________________ parameter symbol conditions min typ max units overshoot and undershoot (note 26) 650 mv level-setting dacs dhv_, dlv_, dtv_, chv_, clv_ 16 resolution n cplv_, cphv_ 12 bits differential nonlinearity dnl ? mv voltage settling time full-scale change to ?.5mv 20 s ground sense (dgs) input range v gs relative to agnd_, verified by functional test -250 +250 mv gain 1 v/v input resistance 1m reference input (note 27) 2.5 v 1k tri-state load (pullup/pulldown) source impedance when enabled tested at -5ma, 0, +5ma using a 0.5ma step 950 1050 maximum source current v dut _ = +6.1v, v dtv _ = -1.1v 6.9 7.2 ma maximum sink current v dut _ = -1.1v, v dtv _ = +6.1v 6.9 7.2 ma turn-on time 60 ns turn-off time 60 ns offset voltage output with no load, v dtv_ = 0 and 3v ?0 mv linearity error no load, v dtv _ = -1.5v to +6.5v ?5 mv temperature monitor nominal voltage t j = +70?, r l 10m 3.43 v temperature coefficient 10 mv/? output resistance 15 k differential control inputs (data_, ndata_, rcv_, nrcv_) input high voltage -1.6 +3.5 v input low voltage -2.0 +3.1 v differential input voltage ?.15 ?.00 v termination resistor 50 to vterm_ 48 52 vterm_ voltage range verified by functional test -2.0 +3.5 v serial port inputs ( cs , sclk, din, rst , load , v dd = 3.3v) input high 2/3 (v dd ) v dd v input low -0.1 1/3 (v dd ) v electrical characteristics (continued) (v cc = +9.75v, v ee = -4.75v, v dd = 3.3v, v dhv_ = +3v, v dlv_ = 0, v dtv_ = +1.5v, sc1 = sc0 = 0, v chv_ = +2.0v, v clv_ = +1.0v, v cphv_ = +7.2v, v cplv_ = -2.2v, v vterm = v t_ = +1.8v, r t = 50 || 1pf, t j = +70?, unless otherwise noted. all temperature coefficients are measured at t j = +40? to +100?, unless otherwise noted.) (note 1)
max9973/max9974 dual driver/comparator/load with internal dacs _______________________________________________________________________________________ 9 parameter symbol conditions min typ max units serial port timing (note 28) sclk frequency 50 mhz sclk pulse-width high t 1 8ns sclk pulse-width low t 2 8ns cs low to sclk high setup t 3 3.5 ns sclk high to cs low hold t 4 3.5 ns cs high to sclk high setup t 5 3.5 ns sclk high to cs high hold t 6 3.5 ns din to sclk high setup t 7 3.5 ns din to sclk high hold t 8 3.5 ns cs high pulse width t 9 20 ns load low pulse width t 10 20 ns rst low pulse width t 11 20 ns cs high to load low hold time t 12 20 ns common functions operating voltage range (note 29) -1.5 +6.5 v 0 < v dut _ < 3v ? v clv _ = v chv _ = +6.5v, v dut _ = -1.5v 5 dut_ high-impedance leakage v clv _ = v chv _ = -1.5v, v dut _ = +6.5v ? ? leak = 1, 0 < v dut _ < 3v, t j < +90? -10 +10 leak = 1, v clv _ = v chv _ = +6.5v, v dut _ = -1.5v, t j < +90? -10 +10 dut_ low-leakage mode leakage leak = 1, v clv _ = v chv _ = -1.5v, v dut _ = +6.5v, t j < +90? -10 +10 na driver in terminate mode 2 dut_ combined capacitance driver in high impedance 4 pf power supply positive supply voltage v cc 9.5 9.75 10.5 v negative supply voltage v ee -5.2 -4.75 -4.5 v logic supply voltage v dd 2.7 3.3 5.0 v positive supply current i cc (note 30) 70 85 ma negative supply current i ee (note 30) 150 180 ma logic supply current i dd (note 30) 1.2 2 ma power dissipation (notes 30, 31) 1.4 1.7 w power dissipation per channel (notes 30, 31) 700 mw electrical characteristics (continued) (v cc = +9.75v, v ee = -4.75v, v dd = 3.3v, v dhv_ = +3v, v dlv_ = 0, v dtv_ = +1.5v, sc1 = sc0 = 0, v chv_ = +2.0v, v clv_ = +1.0v, v cphv_ = +7.2v, v cplv_ = -2.2v, v vterm = v t_ = +1.8v, r t = 50 || 1pf, t j = +70?, unless otherwise noted. all temperature coefficients are measured at t j = +40? to +100?, unless otherwise noted.) (note 1) note 1: all minimum and maximum specifications are 100% production tested, unless otherwise noted. all other test limits are guaranteed by design. tests are performed at nominal supply voltages, unless otherwise noted. tested with t j = +70? with accuracy of ?5?. note 2: guaranteed by design and characterization.
max9973/max9974 dual driver/comparator/load with internal dacs 10 ______________________________________________________________________________________ electrical characteristics (continued) (v cc = +9.75v, v ee = -4.75v, v dd = 3.3v, v dhv_ = +3v, v dlv_ = 0, v dtv_ = +1.5v, sc1 = sc0 = 0, v chv_ = +2.0v, v clv_ = +1.0v, v cphv_ = +7.2v, v cplv_ = -2.2v, v vterm = v t_ = +1.8v, r t = 50 || 1pf, t j = +70?, unless otherwise noted. all temperature coefficients are measured at t j = +40? to +100?, unless otherwise noted.) (note 1) note 3: change in any voltage over operating range. includes both gain and offset temperature effects. simulated over entire operating range. verified at worst-case points, which are the endpoints. v dhv_ - v dlv_ > 250mv. note 4: data_ = 1, v dhv_ = 3v, v dlv_ = 0, v dtv_ = 1.5v, i out = ?0ma. different values within the range of 48 to 52 are available by custom trimming (contact factory). note 5: rise time of the differential inputs data_ and rcv_ is 250ps (10% to 90%). sc1 = sc0 = 0, 40mhz, unless otherwise specified. note 6: 0 to 6v step, current supplied for a minimum of 10ns. note 7: v dtv_ = 1.5v, r s = 50 external signal driven into a transmission line to produce a 0/3v edge at the comparator input with 1.0ns rise time (10% to 90%). measurement point is at comparator input. note 8: measured from the 90% point of the driver output (relative to its final value) to the waveform settling to within the specified limit. note 9: propagation delays are measured from the crossing point of the differential input signals to the 50% point of expected output swing. note 10: measured from crossing point of rcv_/nrcv_ to 50% point of the output waveform. note 11: four measurements are made: dhv_ to high impedance, dlv_ to high impedance, high impedance to dhv_, high imped- ance to dlv_. the worst difference is specified. note 12: four measurements are made: dhv_ to dtv_, dlv_ to dtv_, dtv_ to dhv_, dtv_ to dlv_. the worst difference is specified. note 13: at this pulse width, the output reaches at least 95% of its nominal (dc) amplitude. the pulse width is measured at data_ and ndata_. note 14: maximum data rate in transitions/second. a waveform that reaches at least 95% of its programmed amplitude may be generated at one-half of this frequency. note 15: change in offset at any voltage over operating range. includes both gain (cmrr) and offset temperature effects. note 16: relative to straight line between 0 and 3v. note 17: all propagation delays measured from v dut_ crossing calibrated chv_/clv_ threshold to crossing point of differential outputs. note 18: load is a 500ps transmission line terminated with 1pf and 50 . note 19: all ac specifications are measured with dut_ (comparator input) as the reference. note 20: 40mhz, 0 to 2v input to comparator, reference = 1v, 50% duty cycle, 1ns rise/fall time, z s = 50 , driver in term mode with v dtv_ = 0, unless otherwise noted. note 21: at this pulse width, the output reaches at least 90% of its nominal peak-to-peak swing. the pulse width is measured at the crossing points of the differential outputs. 500ps rise and fall time. timing specs are not guaranteed. note 22: v dut_ = 200mv p-p , rise/fall time = 150ps, overdrive = 100mv, v dtv_ = v cm . valid for common-mode ranges where the signal does not exceed the operating range. specification is worst case (slowest to fastest) over the specified range. note 23: input to comparator is 40mhz at 0 to 1v, 50% duty cycle, 1ns rise time. note 24: this specification is implicitly tested, by meeting the high-impedance leakage specification. note 25: resistance measurements are made using small-signal voltage changes in the loading instrument. absolute value of the difference in measured resistance over the specified range, tested separately for each current polarity. note 26: ripple in the dut_ signal after one round-trip delay. stimulus is 0 to 3v, 2.5v/ns square wave from far end of 3ns transmission line with r s = 25 , clamps set to 0 and 3v. note 27: any deviation from 2.5v affects offset and gain of all levels. note 28: serial port timing specifications are measured at a logic supply voltage (v dd ) of +3.3v, ensuring operation of the serial port at rated speed for v dd from +3.3v to +5.5v. note 29: the maximum usable output operating voltage is limited to -1.5v to +6.5v. externally forced voltages may exceed this range without damage to the device, provided that they are limited per the absolute maximum ratings . external clamps must be provided to limit voltages in this range, or damage to the device is likely. note 30: total for dual device. r l 10m . worst case of the following conditions: driver enabled, lleak = 0; driver disabled, lleak = 0; driver enabled, rcv_ = 1; driver disabled, lleak = 1. note 31: excludes dissipation of comparator output supply. a typical output configuration and v+ = 1.8v adds 30mw (typ) per channel to device power.
max9973/max9974 dual driver/comparator/load with internal dacs ______________________________________________________________________________________ 11 driver small- signal response max9973 toc01 v dut_ = 50mv/div t = 2.0ns/div v dlv_ = 0 r l = 50 v dhv_ = 500mv v dhv_ = 200mv v dhv_ = 100mv 0 driver large- signal response max9973 toc02 v dut_ = 500mv/div t = 2.0ns/div v dlv_ = 0 r l = 50 v dhv_ = 5v v dhv_ = 3v v dhv_ = 1v 0 driver 3v trailing-edge timing error vs. pulse width max9973 toc03 pulse width (ns) timing error (ps) 20 15 10 5 -40 -20 0 20 40 60 80 -60 025 positive pulse normalized at pw = 12.5ns period = 25ns, v dhv_ = +3v, v dlv_ = 0 negative pulse driver 1v trailing-edge timing error vs. pulse width max9973 toc04 pulse width (ns) timing error (ps) 20 15 10 5 -40 -30 -20 -10 0 10 20 30 40 50 -50 025 negative pulse normalized at pw = 12.5ns period = 25ns, v dhv_ = +1v, v dlv_ = 0 positive pulse driver time delay vs. common-mode voltage max9973 toc05 common-mode voltage (v) time delay (ps) 5 4 3 2 1 0 -10 0 10 20 30 40 50 -20 -1 6 falling edge normalized at v cm = +1.5v rising edge drive to term transition max9973 toc06 v dut_ = 250mv/div t = 2.0ns/div 0 dlv_ to dtv_ dhv_ to dtv_ r l = 50 v dhv_ = 3.0v v dtv_ = 1.5v v dlv_ = 0 drive to high impedance transition max9973 toc07 v dut_ = 200mv/div t = 2.0ns/div dhv_ to high impedance dlv_ to high impedance 0 r l = 50 v dhv_ = +1v v dlv_ = -1v driver linearity error vs. output voltage max9973 toc08 v dut_ (v) linearity error (mv) 5.5 4.5 -0.5 0.5 1.5 2.5 3.5 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 -1.5 6.5 dut_ = dhv_ v dlv_ = -1.5v v dtv_ = 0 driver linearity error vs. output voltage max9973 toc09 v dut_ (v) linearity error (mv) 5.5 4.5 -0.5 0.5 1.5 2.5 3.5 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 -1.5 6.5 dut_ = dlv_ v dhv_ = +6.5v v dtv_ = 0 typical operating characteristics (t j = +70?, unless otherwise noted.)
max9973/max9974 dual driver/comparator/load with internal dacs 12 ______________________________________________________________________________________ driver linearity error vs. output voltage max9973 toc10 v dut_ (v) linearity error (mv) 5.5 4.5 -0.5 0.5 1.5 2.5 3.5 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.5 -2.0 -1.5 6.5 dut_ = dtv_ v dhv_ = +6.5v v dlv_ = -1.5v driver gain vs. temperature max9973 toc11 temperature ( c) gain (v/v) 90 80 50 60 70 0.9994 0.9996 1.9998 1.0000 1.0002 1.0004 1.0006 1.0008 0.9992 40 100 normalized at t j = +70 c driver offset vs. temperature max9973 toc12 temperature ( c) offset (mv) 90 80 70 -1.0 -0.5 0 0.5 1.0 2.0 1.5 2.5 -2.0 -1.5 40 50 60 100 normalized at t j = +70 c comparator offset vs. common-mode voltage max9973 toc13 common-mode voltage (v) offset (mv) 5.5 4.5 2.5 3.5 0.5 1.5 -0.5 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2.0 -2.0 -1.5 6.5 other comparator reference = 2.5v normalized at v cm = 1.5v comparator timing variation vs. common-mode voltage max9973 toc14 common-mode voltage (v) timing variation (ps) 5.5 4.5 3.5 2.5 1.5 0.5 -0.5 -10 -5 0 5 10 15 20 -15 -1.5 6.5 normalized at v cm = 1.5v falling edge rising edge comparator waveform tracking max9973 toc15 reference level (%) timing variation (ps) 80 60 40 20 -200 -150 -100 -50 0 50 -250 0100 normalized at 50% reference level v dut_ = 1 to 1v pulse falling edge rising edge comparator trailing-edge timing variation vs. pulse width max9973 toc16 pulse width (ns) timing variation (ps) 20 15 10 5 -20 0 20 40 60 80 -40 025 normalized at pw = 12.5ns high pulse low pulse comparator timing variation vs. input slew rate max9973 toc17 slew rate (v/ns) timing variation (ps) 5 4 1 2 3 -20 -10 0 10 20 30 40 50 -30 06 normalized at sr = 4v/ns v dut_ falling v dut_ rising comparator differential output response max9973 toc18 v dut_ = 100mv/div t = 2.0ns/div 0 double terminated signal v dut_ = 0 to 3v pulse v chv_ = v clv_ = 1.5v typical operating characteristics (continued) (t j = +70?, unless otherwise noted.)
max9973/max9974 dual driver/comparator/load with internal dacs ______________________________________________________________________________________ 13 comparator response to high slew-rate overdrive max9973 toc19 v dut_ = 150mv/div t = 2.0ns/div 0 input slew rate = 4v/ns high impedance output input comparator offset vs. temperature max9973 toc20 temperature ( c) offset (mv) 90 80 70 -1.5 -1.0 -0.5 0 0.5 1.5 1.0 -2.0 40 60 50 100 normalized at t j = +70 c clamp response at source max9973 toc21 600mv/div t = 10ns/div 0 v source_ = 0 to 3v square wave r s = 25 v cplv_ = 0 v cphv_ = +3v high-impedance leakage current vs. dut_ voltage max9973 toc22 v dut_ (v) leakage (na) 5.5 4.5 -0.5 0.5 1.5 2.5 3.5 -40 -20 0 20 40 60 80 100 -60 -1.5 6.5 low leakage current vs. dut_ voltage max9973 toc23 v dut_ (v) leakage (pa) 5.5 4.5 -0.5 0.5 1.5 2.5 3.5 -20 -10 0 10 20 30 -30 -1.5 6.5 clamp current vs. difference voltage max9973 toc24 v cphv_ (v) i dut_ ( a) 3.8 3.6 3.4 3.2 0 200 400 600 800 1000 1200 -200 3.0 4.0 v dut_ = 3v v cplv_ = 0 clamp current vs. difference voltage max9973 toc25 v cplv_ (v) i dut_ (ma) -0.2 -0.8 -0.6 -0.4 -1000 -800 -600 -400 -200 0 200 -1200 -1.0 0 v dut_ = 0 v cphv_ = 3v drive 1v to low leakage transition max9973 toc26 c1 fall 10.12ns c1 high 504mv c1 low 4mv low leakage to drive 1v transition max9973 toc27 c1 rise 815ns c1 high 500mv c1 low 4mv typical operating characteristics (continued) (t j = +70?, unless otherwise noted.) ______________________________________________________________________________________ 13
max9973/max9974 dual driver/comparator/load with internal dacs 14 ______________________________________________________________________________________ positive supply current vs. positive supply voltage max9973 toc28 v cc (v) i cc (ma) 10.3 10.1 9.9 9.7 60.0 60.1 60.2 60.3 60.4 60.5 59.9 9.5 10.5 v dhv_ = +3.0v, v dlv_ = 0, v dtv_ = +1.5v, v cphv_ = +7.2v, v cplv_ = -2.2v, high impedance, v ee = -5.25v negative supply current vs. negative supply voltage max9973 toc29 v ee (v) i ee (ma) -4.6 -4.7 -5.1 -5.0 -4.9 -4.8 134.0 134.5 135.0 135.5 136.0 136.5 137.0 137.5 133.5 -5.2 -4.5 v dhv_ = +3.0v, v dlv_ = 0, v dtv_ = +1.5v, v cphv_ = +7.2v, v cplv_ = -2.2v, high impedance, v cc = +9.75v positive supply current vs. temperature max9973 toc30 temperature ( c) i cc (ma) 90 80 70 60 50 59.5 60.0 60.5 61.0 61.5 62.0 59.0 40 100 v dut_ = v dtv_ = +1.5v, v dhv_ = +3v, v dlv_ = 0, v chv_ = v clv_ = 0, v cphv_ = +7.2v, v cplv_ = -2.2v, v cc = +9.75v, v ee = -5.25v typical operating characteristics (continued) (t j = +70?, unless otherwise noted.) negative supply current vs. temperature max9973 toc31 temperature ( c) i ee (ma) 90 80 50 60 70 133.5 134.0 134.5 135.0 135.5 136.0 136.5 137.0 133.0 40 100 v dut_ = v dtv_ = +1.5v, v dhv_ = +3v, v dlv_ = 0 v chv_ = v clv_ = 0, v cphv_ = +7.2v, v cplv_ = -2.2v, v cc = +9.75v, v ee = -5.25v driver large-signal response into 500 max9973 toc32 v dut_ = 1v/div t = 2.0ns/div v dhv_ = 5v v dhv_ = 3v v dhv_ = 1v 0 v dlv_ = 0 r l = 500 c l = 0.1pf driver 1v 600mbps signal response max9973 toc33 v dut_ = 100mv/div t = 0.5ns/div v dlv_ = 0 v dhv_ = +1v r l = 50 0 driver 1v 1200mbps signal response max9973 toc34 v dut_ = 100mv/div t = 0.5ns/div v dlv_ = 0 v dhv_ = +1v r l = 50 0 driver 3v 600mbps signal response max9973 toc35 v dut_ = 250mv/div t = 0.5ns/div v dlv_ = 0 v dhv_ = +3v r l = 50 0
driver 3v 800mbps signal response max9973 toc36 v dut_ = 250mv/div t = 0.5ns/div v dlv_ = 0 v dhv_ = +3v r l = 50 0 max9973/max9974 dual driver/comparator/load with internal dacs ______________________________________________________________________________________ 15 driver dynamic current-limit response max9973 toc37 i dut_ = 50ma/div t = 50ns/div 0 driver sourcing driver sinking typical operating characteristics (continued) (t j = +70?, unless otherwise noted.) pin description pin (max9973) name function 1, 16, 18, 33, 36, 39, 42, 45, 48, 63 v ee negative power-supply input 2, 15, 24, 35, 37, 44, 46, 57 v cc positive power-supply input 3, 14 agnd analog ground connection 4 ref dac reference input. set to 2.5v with respect to dgs. 5 dgs dut ground sense. dgs is the ground reference for the dacs. connect dgs to ground of the device-under-test. 6 temp temperature monitor output 7, 17, 32, 40, 41, 49, 64 gnd ground 8 cs chip-select input. serial port activation input. 9 sclk serial-clock input. clock for serial port. 10 din data input. serial port data input. 11 v dd digital interface power-supply input 12 load load input. latches serial register data into dacs. 13 rst reset input. asynchronous reset input for the serial register. 19 ndata1 channel 1 multiplexer control input n 20 data1 channel 1 multiplexer control input differential controls data1 and ndata1 select driver 1? input from dhv1 or dlv1. drive data1 above ndata1 to select dhv1. drive ndata1 above data1 to select dlv1. 21 vterm1 channel 1 rcv/nrcv and data/ndata termination voltage input. termination voltage input for the rcv1, nrcv1, data1, and ndata1 differential inputs.
max9973/max9974 dual driver/comparator/load with internal dacs 16 ______________________________________________________________________________________ pin description (continued) pin (max9973) name function 22 nrcv1 channel 1 multiplexer control input n 23 rcv1 channel 1 multiplexer control input differential controls rcv1 and nrcv1 place channel 1 in receive mode. drive rcv1 above nrcv1 to place channel 1 into receive mode. drive nrcv1 above rcv1 to place channel 1 into drive mode. 25, 34, 47, 56 n.c. no connection. make no connection. 26 ncl1 channel 1 low comparator output n 27 cl1 channel 1 low comparator output differential outputs of channel 1 low comparator. 28 v t1 comparator termination voltage input. termination voltage for the comparator output pullup resistors for channel 1. 29 nch1 channel 1 high comparator output n 30 ch1 channel 1 high comparator output differential outputs of channel 1 high comparator. 31 rhyst1 comparator hysteresis programming input for channel 1 38 dut1 channel 1 device-under-test input/output. combined i/o for driver, comparator, clamp, and load. 43 dut0 channel 0 device-under-test input/output. combined i/o for driver, comparator, clamp, and load. 50 rhyst0 comparator hysteresis programming input for channel 0 51 ch0 channel 0 high comparator output 52 nch0 channel 0 high comparator output n differential outputs of channel 0 high comparator. 53 v t0 comparator termination voltage input. termination voltage for the comparator output pullup resistors for channel 0. 54 cl0 channel 0 low comparator output 55 ncl0 channel 0 low comparator output n differential outputs of channel 0 low comparator. 58 rcv0 channel 0 multiplexer control input 59 nrcv0 channel 0 multiplexer control input n differential controls rcv0 and nrcv0 place channel 0 in receive mode. drive rcv0 above nrcv0 to place channel 0 into receive mode. drive nrcv0 above rcv0 to place channel 0 into drive mode. 60 vterm0 channel 0 rcv/nrcv and data/ndata termination voltage input. termination voltage input for the rcv0, nrcv0, data0, and ndata0 differential inputs. 61 data0 channel 0 multiplexer control input 62 ndata0 channel 0 multiplexer control input n differential controls data0 and ndata0 select driver 0? input from dhv0 or dlv0. drive data0 above ndata0 to select dhv0. drive ndata0 above data0 to select dlv0. ?p exposed heat removal paddle. the paddle is electrically isolated from the die. make no electrical connection to ep.
max9973/max9974 dual driver/comparator/load with internal dacs ______________________________________________________________________________________ 17 figure 1. functional diagram max9973 max9974 cs sclk serial interface serial interface common to both channels 24 din to dcl and dacs rst load ref dhv_ dac dlv_ dtv_ dhv_ lden_ v cc v ee v dd temp gnd agnd dgs dut_ lden_ tmsel_ dcl_ mode control multiplexer lleak_ s1_ s0_ slew-rate control buffer tmsel_ 4 x 50 4 x 50 clamps comparators high impedance 0 0 1 1 dtv_ dac cphv_ dac chv_ dac one of two identical channels shown cplv_ dac dlv_ dac load 1000 50 lleak_ data_ ndata_ rcv_ nrcv_ ch_ nch_ vterm_ vt_ - + clv_ dac cl_ ncl_ - + s1_ s0_
max9973/max9974 dual driver/comparator/load with internal dacs 18 ______________________________________________________________________________________ detailed description the max9973/max9974 are fully integrated, high-per- formance, dual-channel pin electronics driver/compara- tor/load (dcl) with built-in level-setting dacs. each channel includes a three-level pin driver with three level- setting dacs, a window comparator with two level-setting dacs, two dynamic clamps with two level-setting dacs, and a 1k load driven by the driver? dtv_ dac. figure 1 shows a functional diagram of the max9973/max9974. the three-level pin driver features a wide -1.5v to +6.5v voltage range and includes high-impedance and active- termination (3rd-level drive) modes. high-speed differen- tial multiplexer control inputs data and rcv with internal termination resistors switch the driver between the three input levels. figure 2 shows a block diagram of the sim- plified driver channel. the window comparators provide extremely low timing variation. the max9973g/max9974g comparator open- collector outputs sink 8ma (typ), while the max9973h/ max9974h comparator outputs sink 16ma (typ). figure 3 shows the comparator function. the dynamic clamps provide damping of high-speed dut waveforms when high-impedance receive mode is selected. the loads facilitate fast contact testing when used in con- junction with the comparators. loads also function as pullups for a device-under-test that has open-drain/col- lector outputs. a serial interface configures the device and its functions. the max9973/max9974 are available in a 64-pin (10mm x 10mm x 1.00mm) tqfp-ep package with an exposed paddle on top (max9973) or bottom (max9974) for heat removal. power dissipation is only 700mw per channel. the full operating voltage range is -1.5v to +6.5v. operation is specified with an internal die temperature of +40? to +100?. the devices feature a temperature monitor output. output driver the driver input is a high-speed multiplexer that selects one of three dac voltages: dhv_, dlv_, or dtv_. the high-speed differential inputs data_/ndata_ and rcv_/nrcv_, and mode-control bit tmsel_ control the max9973 max9974 slew rate buffer clamps 0 1 comparators and load cphv_ dac cplv_ dac dcl mode control bits tmsel_ sc0_ sc1_ lleak_ high impedance 4 dut_ 0 0 1 1 0 50 4 x 50 high-speed inputs data_ ndata_ vterm_ + - rcv_ nrcv_ + - dlv_ dac dhv_ dac dtv_ dac figure 2. simplified driver channel
max9973/max9974 dual driver/comparator/load with internal dacs ______________________________________________________________________________________ 19 switching between the dac voltages (table 1). a slew- rate circuit controls the slew rate of the buffer input with one of four possible slew rates selectable (table 2). the 100% slew rate is a function of the inherent speed of the multiplexer (see the driver large-signal response graph in the typical operating characteristics ). dut_ can be toggled at high speed between driver and high-imped- ance modes, or can be placed into low-leakage mode table 1. driver channel logic high-speed inputs mode control bits data_/ndata_ rcv_/nrcv_ tmsel_ (d3) lleak_ (d2) dut_ data_ > ndata_ rcv_ < nrcv_ x 0 dhv_ data_ < ndata_ rcv_ < nrcv_ x 0 dlv_ x rcv_ > nrcv_ 1 0 dtv_ x rcv_ > nrcv_ 0 0 high impedance (clamps engaged) x x x 1 low leakage max9973g max9974g 4 x 50 v ee ch_ nch_ v t _ cl_ ncl_ chv_ dac 8ma 8ma dut_ - + clv_ dac + - figure 3. comparator functional diagram table 2. driver slew-rate logic mode control bits s1_ (d1) s0_ (d0) driver slew rate (%) 0 0 100 (fastest) 01 75 10 50 1 1 25 (slowest) table 3. comparator logic comparator inputs comparator outputs h igh c o m pa r at o r l o w c o m pa r at o r d u t _ > c h v_ d u t _ > c l v_ ch_ nch_ cl_ ncl_ 000101 010110 101001 111010 x = don? care.
max9973/max9974 dual driver/comparator/load with internal dacs 20 ______________________________________________________________________________________ using mode control bit lleak_ (figure 2, table 1). in high-impedance mode, the bias current at dut_ is less than 5? over the -1.5v to +6.5v range, while the node maintains its ability to track high-speed signals. in low- leakage mode, the bias current at dut_ is further reduced to less than ?0na, and signal tracking slows. see the low-leakage mode section for more details. the nominal driver output resistance is 50 . contact the factory for different resistance values within the 48 to 52 range. clamps the voltage clamps (high and low) limit the voltage at dut_ and suppress reflections when the channel is con- figured as a high-impedance receiver. the clamps behave as diodes with series 50 resistors connected to the outputs of high-current buffers. internal circuitry com- pensates for the diode drop at 1ma clamp current. set the clamp voltages using dacs cphv_ and cplv_. the clamps are enabled only when the driver is in high- impedance mode (figure 2). for transient suppression, set the clamp voltages to approximately the minimum and maximum expected dut_ voltage range. the optimal clamp voltages are application-specific and must be empirically determined. if clamping is not desired, set the clamp voltages at least 0.7v outside the expected dut_ voltage range; overvoltage protection remains active without loading dut_. comparators the max9973/max9974 provide two independent high- speed comparators for each channel. each comparator has one input connected internally to dut_ and the other input connected to either dac chv_ or dac clv_ (see figures 1 and 3). comparator outputs are a logical result of the input conditions, as indicated in table 3. the comparator differential outputs are open- collector to ease interfacing with a wide variety of logic families. the max9973g/max9974g switch an 8ma current sink between the two outputs, while the d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 max9973 max9974 register data latch latch latch register address write enable ch0 write enable ch1 unused unused write enable_ 1 4 5 5 16 1 4 16 1 4 16 address data cs write enable_ address data cs cs write enable_ address data dcl_ mode control bits 5 load dhv_ dac data data 16 data load clv_ dac load dhv_ clv_ sclk din rst cs load enable figure 4. serial interface block diagram
max9973/max9974 dual driver/comparator/load with internal dacs ______________________________________________________________________________________ 21 max9973h/max9974h switch 16ma. the 50 output termination resistors connect to voltage input v t _. each output provides a nominal 400mv p-p swing and 50 source termination. 1k load the 1k load is a resistor connected to dut_ from the output of an internal buffer. the buffer? input is dac dtv_ (figure 1). the buffer sinks and sources at least 6.9ma. a switch separates the resistor from the buffer. operate the switch with serial control bits lden_, lleak_, and tmsel_, and through high-speed differ- ential input rcv_/nrcv_. table 4 shows the truth table for the load-switch operation. dut ground-sense input the dut ground-sense input (dgs) senses the ground potential of the device-under-test and allows the output and dac levels of the max9973/max9974 to be set rel- ative to that ground potential. connect dgs to the ground of the device-under-test. low-leakage mode asserting lleak_ through the serial interface or with the digital input rst places the max9973/max9974 in a very low-leakage state (see the electrical characteristics table). with lleak_ asserted, the comparators, driver, clamps, and active load are disabled. this mode is con- venient for making iddq and pmu measurements with- out the need for an output disconnect relay. lleak_ is programmed independently for each channel, while rst acts on both channels simultaneously. serial interface and device control a cmos-compatible serial interface controls the max9973/max9974 modes (figure 4, table 5). control data flow into a 24-bit shift register and is latched when cs is taken high, as shown in figure 5. the first eight bits, a7?0, determine which of the two channels is being commanded, and which dac or dcl the follow- ing 16 bits program. the 16 bits, d15?0, set the dac voltage or control the setup of the max9973/max9974 through the mode control bits, as shown in tables 5, 6, 7, and figure 6. table 5. serial interface data bit definitions din bit bit function a7 not used a6 not used a5 write enable channel 1 a4 write enable channel 0 a3 a2 a1 a0 register address (table 6) d15?0 register data table 7. dcl mode control bits bit name function power-up state d4 lden load enable 0 d3 tmsel terminate select 0 d2 lleak low-leakage enable 1 d1 s1 0 d0 s0 slew-rate control (table 2) 0 table 6. register addresses register address bits a3 a2 a1 a0 register function 0 0 0 0 dcl mode 0 0 0 1 dhv_ level 0 0 1 0 dlv_ level 0 0 1 1 dtv_ level 0 1 0 0 chv_ level 0 1 0 1 clv_ level 0 1 1 0 cphv_ level 0 1 1 1 cplv_ level 1 x x x not used table 4. load logic high-speed input mode control bits rcv_/nrcv_ lleak_ (d2) tmsel_ (d3) lden_ (d4) load rcv_ < nrcv_ 0 x x off x0x0off rcv_ > nrcv_ 0 0 1 on rcv_ > nrcv_ 0 1 1 off x1xxoff x = don? care.
max9973/max9974 dual driver/comparator/load with internal dacs 22 ______________________________________________________________________________________ high-speed differential inputs rcv_/nrcv_ and data_/ndata_, in conjunction with control bits tmsel_, lleak_, and lden_, manage the features of each channel. rst sets lleak = 1 for both channels, forcing both channels into low-leakage mode; all other bits are unaffected. at power-up, hold rst low until v cc and v ee have stabilized. serial communication figure 5 and the serial port timing section of the electrical characteristics table show the serial interface timing requirements. note that the first rising clock edge, after cs goes low, shifts in bit a7, and the last rising clock edge latches in bit d0. forcing load low then transfers the data from the serial input register to the dacs and dcls. sclk load rst din t 4 t 3 cs t 12 t 10 t 6 t 5 t 9 t 1 t 2 t 11 t 7 a7 a0 d15 d0 t 8 figure 5. serial-interface timing
max9973/max9974 dual driver/comparator/load with internal dacs ______________________________________________________________________________________ 23 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dcl dhv dtv dlv chv clv cphv cplv see tables 1, 2 and 4 for mode settings dhv level = (dac setting x 152.59 v) - 2.5v dtv level = (dac setting x 152.59 v) - 2.5v dlv level = (dac setting x 152.59 v) - 2.5v chv level = (dac setting x 152.59 v) - 2.5v clv level = (dac setting x 152.59 v) - 2.5v cphv level = (dac setting x 2.4414mv) - 2.5v cplv level = (dac setting x 2.4414mv) - 2.5v reserved set to zeros dac setting dac setting dac setting dac setting dac setting dac setting dac setting mode bits unused unused figure 6. register data for dcl and dac programming dacs as driver channel inputs digital-to-analog converters, programmed through the serial interface, provide input voltages to the three input multiplexers (dhv_, dtv_, and dlv_), the clamps (cphv_ and cplv_), the comparators (chv_ and clv_), and the load (dtv_ doubles as the load input voltage source). set the dac output voltages as detailed in figure 6. temperature monitor the max9973 supplies a temperature output signal, temp, that asserts a nominal output voltage of 3.43v at a die temperature of +70? (343k). the output voltage changes proportionally with temperature at 10mv/?, but is not calibrated. heat removal under normal circumstances, the max9973 requires heat removal through the exposed paddle through the use of an external heat sink. the exposed paddle is electrically isolated from the die. make no electrical connection to the exposed paddle. power-supply considerations bypass all v cc and v ee power pins each with a 0.01? capacitor, and use bulk bypassing of at least 10? on each supply.
max9973/max9974 dual driver/comparator/load with internal dacs 24 ______________________________________________________________________________________ chip information process: bicmos 64 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 gnd 63 v ee 62 ndata0 61 data0 60 vterm0 59 nrcv0 58 rcv0 57 v cc 56 n.c. 55 ncl0 54 cl0 53 v t0 52 nch0 51 ch0 50 rhyst0 49 gnd v ee n.c. v cc v ee v cc dut0 v ee gnd gnd v ee dut1 v cc v ee v cc n.c. v ee 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v ee v cc agnd ref dgs temp gnd cs sclk din v dd load rst agnd v cc v ee 17 gnd 18 v ee 19 ndata1 20 data1 21 vterm1 22 nrcv1 23 rcv1 24 v cc 25 n.c. 26 ncl1 27 cl1 28 v t1 29 nch1 30 ch1 31 rhyst1 32 gnd max9973 tqfp-ep-idp pin configuration
max9973/max9974 dual driver/comparator/load with internal dacs ______________________________________________________________________________________ 25 64l tqfp.eps a 1 2 21-0162 package outline, 64l tqfp, 10x10x1.00mm exposed pad option, inverted die pad package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 26 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. a 2 2 21-0162 package outline, 64l tqfp, 10x10x1.00mm exposed pad option, inverted die pad dual driver/comparator/load with internal dacs max9973/max9974 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs max9973 part number table notes: see the max9973 quickview data sheet for further information on this product family or download the max9973 full data sheet (pdf, 380kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis max9973gc c b+td 0c to +70c rohs/lead-free: yes max9973gc c b-d 0c to +70c rohs/lead-free: no max9973gc c b-td 0c to +70c rohs/lead-free: no max9973gc c b+d tqfp;64 pin;10x10x1mm dwg: 21-0084c (pdf) use pkgcode/variation: c 64e+13r * 0c to +70c rohs/lead-free: yes materials analysis didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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